-- $Id: $
-- File name:   SHIFT_REG.vhd
-- Created:     10/4/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Design Entry
-- Description: SHIFT_REG


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity SHIFT_REG is
  port(
          CLK : in std_logic;
        RST_N : in std_logic;
 SHIFT_ENABLE : in std_logic;
       D_ORIG : in std_logic;
       CHK_IN : in std_logic;
     RCV_DATA : out std_logic_vector (7 downto 0));
end SHIFT_REG;



ARCHITECTURE dataflow OF SHIFT_REG IS
       signal present_val : std_logic_vector(7 downto 0);
       signal next_val : std_logic_vector(7 downto 0);
       signal SHIFT_ENABLE_temp : std_logic;

       signal TEMP_val : std_logic_vector(5 downto 0);

BEGIN
   REG_SHFT: process (CLK, RST_N)
   begin
    --present_val <= "00000000";
    if (RST_N = '0') then
      present_val <= "00000000";
    elsif (CLK'event and CLK='1') then
      present_val <= next_val;
    end if; 
   end process;


--Can't remember why I put an extra filp-flop BUT I DO REMEMBER that it helped!
   Delay_SE: process (CLK, RST_N)
   begin
     if (RST_N='0') then
       SHIFT_ENABLE_temp <= '1';
     elsif (CHK_IN='1') then
       SHIFT_ENABLE_temp <= '0';
     elsif (CLK'event and CLK='1') then
       SHIFT_ENABLE_temp <= SHIFT_ENABLE;
     end if;
   end process Delay_SE;


--    REGTWO: process (D_ORIG, SHIFT_ENABLE)
--    begin
--    next_val <= present_val;
--    --next_val <= "00000000";
--    if (SHIFT_ENABLE='1') then
--      next_val <= D_ORIG & present_val(7 downto 1);
--    else
--      next_val <= present_val;
--    end if;
--    end process;

    next_val <= D_ORIG & present_val(7 downto 1) when SHIFT_ENABLE_temp='1'
               else present_val;

--Version 0
--     RCV_DATA <= present_val(7 downto 0);

--Version 1
--     if ( (present_val(7 downto 2) = "000000") or (present_val(7 downto 2) = "111111") ) then
--       RCV_DATA <= (not present_val(7)) & present_val(7 downto 1);
--     else
--       RCV_DATA <= present_val(7 downto 0);
--     end if;

--Version 2
-- --     if (present_val(7 downto 2) = present_val(2 upto 7) ) then
-- --       RCV_DATA <= (not present_val(7)) & present_val(7 downto 1);
-- --     else
-- --       RCV_DATA <= present_val(7 downto 0);
-- --     end if;

--Version 3
 TEMP_val <= present_val(2) & present_val(3) & present_val(4) & present_val(5) & present_val(6) & present_val(7);
-- TEMP_val <= present_val(2 to 7);
--  if (present_val(7 downto 2) = TEMP_val ) then
--    RCV_DATA <= (not present_val(7)) & present_val(7 downto 1);
--  else
--    RCV_DATA <= present_val(7 downto 0);
--  end if;

  RCV_DATA <= present_val(7 downto 0);
end dataflow;


--FROM THE RCU:
-- if ( (RCV_DATA(7 downto 2) = "000000") or (RCV_DATA(7 downto 2) = "111111") ) then
--   CHK <='1';
--   --RCV_DATA <= (not RCV_DATA(7)) & RCV_DATA(7 downto 1);
-- end if;

